Cmsemicon BAT32G1 9 Series, Руководство пользователя

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BAT32G1x9 user manual | Chapter 10 Timer M
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10.3.11 Timer M controls register i (TMCRi) (i=0, 1).
The TMCR1 register is not used in reset synchronous PWM mode and PWM3 mode.
Fig. 10-15 Format of timer M control register i (TMCRi) (i=0, 1) [input capture function and output
comparison function]
Address: 0x40042A70 (TMCR0), 0x40042A80 (TMCR1) after reset: 00H R/W
symbol
TMCRi
CCLR2 CCLR1 CCLR0
Clear selection for the TMi counter
0 0 0
Purge is prohibited (free-running).
0 0 1
Clear when TMGRAi's input capture/comparison matches.
0 1 0 Clear when input capture/comparison matches for TMGRBi.
0 1 1
Synchronous clearing (and clearing at the same time as counters
of other timers Mi) Note 1
1 0 1 Clears when input capture/compare matches for TMGRCi.
1 1 0 Clears when TMGRDi's input capture/compare matches.
Other than the above Prohibit settings.
CKEG1 CKEG0
Select
note 2
for the external clock edge
0 0
Count on the rising edge.
0 1
Count on the falling edge.
1 0
Count on the bilateral edge.
Other than the
above Prohibit settings.
TCK2 TCK1 TCK0
Count the selection of sources
0 0 0
f
CLK
0
0 1
f
CLK
/2
0 1 0
f
CLK
/4
0 1 1
f
CLK
/8
1 0 0
f
CLK
/32
1 0 1
Input
note 3
for TMCLK
Other than the above Prohibit settings.
Note 1. Valid when the TMSYNC bit of the TMMR register is "1" (TM0 and TM1 run synchronously).
2. The TCK2~TCK0 bit is "101B" (the input to TMCLK) and the STCLK bit is "1" Valid when (external clock input
valid).
3. Valid when the STCLK bit of the TMFCR register is "1" (the external clock input is valid).
7 6 5 4 3 2 1 0
CCLR2 CcLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0