Cmsemicon BAT32G1 9 Series, Руководство пользователя

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BAT32G1x9 user manual | Chapter 10 Timer M
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332 / 1149 Rev.1.02
Figure 10-18 Format of Timer M Control Register 0 (TMCR0) [Complementary PWM Mode].
Address: 0x40042A70 after reset: 00H R/W
symbol
TMCR0
CCLR2 CCLR1 CCLR0
Clear selection for the TM0 counter
Must be set to "000B" (No Purge (Free Run)).
CKEG1 CKEG0 Select
Notes 1 and 2
for the external clock edges
0 0
Count on the rising edge.
0
1
Count on the falling edge.
1 0
Count on the bilateral edge.
Other than the above Prohibit settings.
TCK2 TCK1 TCK0
Count the selection of sources
0
0 0
f
CLK
0 0 1
f
CLK
/2
0 1 0
f
CLK
/4
0 1 1
f
CLK
/8
1 0 0
f
CLK
/32
1 0 1
Input
note 3
for TMCLK
Other than the above Prohibit settings.
Note 1. The TCK2~TCK0 bit is "101B" (the input to TMCLK
) and
the STCLK bit is "1" Valid when (external clock
input valid).
2. TCK0 to TCK2 bits, CKEG0 bits, CKEG0 bits, and CKEG1 registers must be given
to TMCR0
registers and
TCKCR1
registers
The bits set the same value.
3. Valid when the STCLK bit of the TMFCR
register is
"1" (the external clock input is valid).
7 6 5 4 3
2 1
0
CCLR2 CcLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0