471
Chapter 14
Queued CSI (CSI30, CSI31)
User’s Manual U16702EE3V2UD00
(4)
Receive Data Buffer Registers (SIRB0, SIRB1)
The SIRB register is a 16-bit register or separated as upper 8 bits (SIRBH) and lower 8 bits
(SIRBL), that is used to store receive data. This register can be read in 8-bit or 16-bit units and is
initialized to 0000H by reset.
Figure 14-5:
Receive Data Buffer Registers (SIRB0, SIRB1) Format
Caution:
The receive data buffer register is considered as emptied by the application software
whenever the lower 8 bits of the register are read. It is therefore necessary to read
SIRBH before SIRBL when 8-bit access is used.
(5)
Chip Select Data Buffer Registers (SFCS0, SFCS1)
The SFCS register is a 16-bit register, or separated as upper 8 bits (SFCSH) and lower 8 bits
(SFCSL), that stores Chip Select data. This register is read/write-enabled and is accessible in
8-bit or 16-bit units. Initial value is FFFFH by reset.
Following the FIFO write pointer, the value written to SFCS is stored in the FIFO data buffer as
Chip Select bits. The value is stored to these bits when the transmit data is written to its register
(SFDB or SFDBL).
SFCS write is prohibited when POWER = 1 and f
QCSI
is stopped.
Figure 14-6:
Chip Select Data Buffer Registers (SFCS0, SFCS1) Format
Caution:
The Chip Select register is stored in the FIFO buffer when the transmit data is written
to its register. It is therefore necessary to write the SFCS register before the SFDB
(SFDBL) register.
Remark:
The active level for each chip select is defined in the CSILn register (CSA[3:0] bits)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
R/W
Initial
value
SIRBn
(n=0, 1)
FFFF FD42H,
FFFF FD62H
R/W 0000H
SIRB15 - SIRB0
Data received from the SIO serial shift register.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
R/W
Initial
value
SFCSn
(n=0, 1)
-
-
-
-
-
-
-
-
-
-
-
-
SFCS
3
SFCS
2
SFCS
1
SFCS
0
FFFF FD44H,
FFFF FD64H
R/W FFFFH
SFCSm
Chip Select Output Selection (m=0 to 3)
0
Output an active level at the CS3nm pin during the data transfer
1
Output an inactive level at the CS3nm pin during the data transfer
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