476
Chapter 14
Queued CSI (CSI30, CSI31)
User’s Manual U16702EE3V2UD00
14.3 Explanation of Queued CSI Functions
14.3.1 Transmit
Buffer
Chip select data and transmission data can be stored to the transmit FIFO buffer continuously by
writing to the SFCS register and SFDB register. The Writing FIFO pointer is automatically incremented
when data is written to SFDB. The size of the transmit FIFO buffer is 20 bits
×
16 entries.
In slave mode, chip select data does not need to be set.
The transfer start condition (SFEMP = 0) is to write to the lower bits of SFDB register. If the transmis-
sion data length is 9 bits or more, data should be written by a 16-bit write to SFDB or by two 8-bit writes
to first SFDBH, then SFDBL (in that order). When transmission data length is 8 bits, data should be set
by one 8-bit write to SFDBL or by one 16-bit write to SFDB. For the 16-bit write the upper 8 bits are
ignored in the 8-bit transmission.
The SFFUL bit in the SFA status register is set “1” after 16 writes have been made to the transmit buffer,
assuming the Writing FIFO pointer was reset previously.
When a transmission write is attempted while the FIFO is full (SFFUL=1), the interrupt INTC3nO is gen-
erated to indicate an overflow. In that case, the transmission and chip select data are discarded and not
stored.
When a transfer cycle is finished and the SIO Loading FIFO pointer is incremented, the FIFO buffer of
the previous location is considered empty in case of single buffer transfer mode. Refer to section 14.3.8
on page 483 for more information on FIFO buffer transfer mode.
Figure 14-11:
Transmit Buffer
SFCS
3, 2, 1, 0
SFCS register
SFDB
15, 14, 13, ......2, 1, 0
SFDB register
SFP
3, 2, 1, 0
SFA register
INC
INC
SIO Loading
FIFO pointer
Writing FIFO
pointer
19
16 15
0
CS
Data
3, 2, 1, 0
15, 14, 13, ......
2, 1, 0
15
14
13
12
11
10
9
8
7
6
5
4
CS data 3
3
CS data 2
Transmission data 2
2
CS data 1
Transmission data 1
1
CS data 0
Transmission data 0
0
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