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Chapter 6
Clock Generator
User’s Manual U16702EE3V2UD00
6.5 Programmable Clock output Function (PCL)
It is possible to output a clock independent from CPU clock on pin P913/TIP20/TOP20/INTP4/PCL. The
programmable clock output frequency is equal to f
PLL_MCKSEL
divided by two prescalers (PCLM and
OCKS3 registers). Corresponding ports registers have to be set accordingly (Refer to section
4.3
”Port Configuration” on page 107
).
6.5.1 Control
registers
(1)
Programmable clock mode register (PCLM)
This is an 8-bit register that controls the PCL output. This register can be read or written in 8-bit or
1-bit units.
Figure 6-16:
Programmable Clock Mode Register (PCLM) Format
Caution:
PCLE can set to 1 after setting the port control registers (PM, PMC, PFC, PFCE).
This bit can set to 1 on PLL operation. And this bit has to be cleared to 0 before
stopping the PLL.
Caution:
Before modifying the output selection clock, PCL output has to be stopped (PCLE bit
cleared to 0).
Symbol
7
6
5
4
3
2
1
0
Address
After reset
PCLM
0
0
0
PCLE
0
PCK2
PCK1
PCK0
FFFFF82FH
01H
R/W
R
R
R
R/W
R
R/W
R/W
R/W
PCLE
PCL operation selection
0
PCL output disable (PCL output level is low)
1
PCL output enable
PCK2
PCK1
PCK0
PLL output select
0
0
0
f
PCL1
=
f
PLL_MCKSEL
0
0
1
f
PCL1
=
f
PLL_MCKSEL
/ 2
0
1
0
f
PCL1
=
f
PLL_MCKSEL
/ 4
0
1
1
f
PCL1
=
f
PLL_MCKSEL
/ 8
1
0
0
f
PCL1
=
f
PLL_MCKSEL
/ 16
1
0
1
Setting prohibited
1
1
0
1
1
1
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