NEC V850E/RS1, User Manual, Page: 481 / 852

481
Chapter 14 Queued CSI (CSI30, CSI31)
User’s Manual U16702EE3V2UD00
14.3.7 Description of the Single Buffer Transfer Mode
Figure 14-17: Single Buffer Transfer Mode Data Handling
Transfer start condition in single buffer transfer mode:
[CTXE = 1 or CRXE = 1] and
[Data exists in FIFO (SFEMP = 0)]
A transfer starts once the transmission data (pointed to by the SIO Loading FIFO pointer) is transferred
from the FIFO buffer to the serial shift register SIO. At that time, the transfer status flag CSOT turns to
“1”. The CS3n[3:0] pins output the chip select data from the FIFO buffer.
At the end of the transfer:
(A) If SIRB is empty, the received data is stored from SIO to SIRB, and transfer end interrupt signal
INTC3nI is generated (in transmit only mode, INTC3nI will be generated only when the FIFO buffer
becomes empty). Finally, the SIO L7oading FIFO pointer is incremented.
(B) If SIRB is not empty, the storing of receive data, INTC3nI generation and SIO Loading FIFO
pointer incrementing wait for the SIRB to be emptied by a software read operation.
(C) In transmit only mode, if transmission data is available in the FIFO buffer, the next transfer will start
immediately, regardless of the SIRB buffer condition.
19 16 15 0
CS Data
3, 2, 1, 0 15, 14, 13, ...... 2, 1, 0
15
14
13
12
11
10
9
8
7
6
CS data 5 5
CS data 4 Transmission data 4 4
CS data 3 Transmission data 3 3
CS data 2 Transmission data 2 2
CS data 1 Transmission data 1 1
CS data 0 Transmission data 0 0
SFCS
3, 2, 1, 0
SFCS register
SFDB
15, 14, 13, ......2, 1, 0
SFDB register
SFA register
INC
INC
SIO Loading
FIFO pointer
Writing FIFO
pointer
CS3n3 to CS3n0 pins
SIO
SIRBE
SO3n pin
SIRB
SFP
3, 2, 1, 0
Diff
SI3n pin
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