811
Chapter 27
Electrical Specification
User’s Manual U16702EE3V2UD00
27.8.7 Bus interface timing (µPD70F3403, µPD70F3403A only)
CLKOUT Asynchronous (4.5 V
≤
V
DD0
=V
DD1
=BV
DD
≤
5.5 V)
Notes: 1.
T= t
CYK
2.
n shows the number of the wait clocks which is inserted in the bus cycle.
In programmable wait insertion, sampling timing changes.
3.
i shows idle state's number (0 or 1) which is inserted after the lead cycle.
4.
This product doesn’t support CLKOUT synchronous mode.
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Address setting time (to ASTB
↓
)
<14>
T
SAST
0.5T-10
-
ns
Address maintenance time (to ASTB
↓
) <15>
T
HSTA
0.5T-10
-
ns
RD
↓ →
Address float delay time
<16>
T
FRDA
-
0
ns
Address
→
Data input setting time
<17>
T
SAID
-
(2+n)T-25
ns
RD
↓ →
Data input setting time
<18>
T
SRDID
-
(1+n)T-20
ns
ASTB
↓ →
RD, WRn
↓
delay time
<19>
T
DSTRDWR
0.5T-10
-
ns
Data input hold time (to RD
↑
)
<20>
T
HRDID
0
-
ns
RD
↑
→
Address output time
<21>
T
DRDA
(1+i)T-10
-
ns
RD, WRn
↑
→
ASTB
↑
delay time
<22>
T
DRDWRST
0.5T-10
-
ns
RD
↑
→
ASTB
↓
delay time
<23>
T
DRDST
(1.5+i)T -10
-
ns
RD, WRn low level width
<24>
T
WRDWRL
(1+n)T-15
-
ns
ASTB high level width
<25>
T
WSTH
T-10
-
ns
WRn
↓ →
Data output time
<26>
T
DWROD
-
10
ns
Data output setting time (to WRn
↑
)
<27>
T
SODWR
(1+n)T-15
-
ns
Data output hold time (to WRn
↑
)
<28>
T
HWROD
T-10
-
ns
WAIT setting time (to Address)
<29>
T
SAWT1
n
≥
1
-
1.5T-30
ns
<30>
T
SAWT2
-
(1.5+n)T-30
ns
WAIT maintenance time (to Address)
<31>
T
HAWT1
n
≥
1
(0.5+n)T
-
ns
<32>
T
HAWT2
(1.5+n)T
-
ns
WAIT setting time (to ASTB
↓
)
<33>
T
SSTWT1
n
≥
1
-
T-20
ns
<34>
T
SSTWT2
-
(1+n)T-20
ns
WAIT maintenance time (to ASTB
↓
)
<35>
T
HSTWT1
n
≥
1
NT
-
ns
<36>
T
HSTWT2
(1+n)T
-
ns
HLDRQ high level width
<37>
T
WHQH
T+10
-
ns
HLDAK low level width
<38>
T
WHAL
T-10
-
ns
HLDAK
↑
→
Bus output delay time
<40>
T
DHAC
-3
-
ns
HLDRQ
↓ →
HLDAK
↓
delay time
<41>
T
DHQHA1
-
(2.5+n)T+20 ns
HLDRQ
↑
→
HLDAK
↑
delay time
<42>
T
DHQHA2
0.5T
1.5T+20
ns
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