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Chapter 14
Queued CSI (CSI30, CSI31)
User’s Manual U16702EE3V2UD00
(2)
Queued CSI Operation Mode Registers (CSIM0, CSIM1)
The CSIM registers control the Queued CSI macro's operations.
These registers can be read or written in 1-bit and 8-bit units.
TRMD, DIR, CSIT, CSWE, CSMD bits can only be written when CTXE = 0 and CRXE = 0.
The registers are initialized to 00H at reset.
Figure 14-2:
Queued CSI Operation Mode Registers (CSIM0, CSIM1) Format (1/2)
Caution:
When changing the POWER bit, do not change any other bit at the same time.
While POWER=”0”, the only registers that can be accessed are CSIM, SFDB, SFDBL,
and SFA.
Set the POWER bit before writing any of the other bits of CSIMn.
Caution:
Write is permitted only when CTXE = 0 and CRXE = 0.
Symbol
7
6
5
4
3
2
1
0
Address
R/W
After
reset
CSIMn
(n = 0, 1)
POWER CTXE
CRXE
TRMD
DIR
CSIT
CSWE
CSMD
FFFFFD40H,
FFFFFD60H
R/W 00H
POWER
Queued CSI operation clock control
0
Stop macro operation clock (Reset internal control circuits)
1
Provide macro operation clock
Clearing POWER = "0" resets the internal circuits asynchronously, stops operation and sets the
Queued CSI to standby state. Input clock is not provided to internal circuits.
Set POWER = "1" to activate the Queued CSI.
CTXE
Transmission enable/disable
0
Transmission disabled
1
Transmission enabled
CRXE
Receive enable/disable
0
Receive disabled
1
Receive enabled
TRMD
Transfer mode select
0
Single buffer transfer mode
1
FIFO buffer transfer mode
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