234
Chapter 6
Clock Generator
User’s Manual U16702EE3V2UD00
6.2 Configuration
Figure 6-1:
Clock Generator
(1)
Main clock oscillator (Main OSC)
The main resonator oscillates the following frequencies (f
X
).
•
In clock-through mode
f
X
= 4 to 8 MHz (internal f
XX
= 4 to 8 MHz)
•
In PLL mode
f
X
= 4 to 8 MHz (internal f
XX
= 4 to 40 MHz (µPD70F3403 and µPD70F3403A)
= 4 to 32 MHz (µPD70F3402))
(2)
PLL
This circuit multiplies the clock generated by the main clock oscillator (f
X
).
It operates in two modes: clock-through mode in which f
X
is output as is, and PLL mode in which a
multiplied clock is output. These modes can be selected by using the SELPLL bit of the Main
peripheral clock control register (MPCCTL). Operation of the PLL can be started or stopped by the
STPPLL bit of MPCCTL register.
(3)
Ring-OSC
Outputs a frequency (f
R
) of 100 to 400 kHz.
(4)
Prescaler 1 (PRS1)
This prescaler divides the clock to be supplied to the WDT2 and the on-chip peripheral functions.
(5)
Prescaler 2 (PRS2)
This circuit divides main clock f
XX
(f
XX
, f
XX
/2, f
XX
/4, f
XX
/8, f
XX
/16, f
XX
/32) to provide the CPU (f
CPU)
clock and system clock (f
CLK
).
f
CLK
is supplied to the interrupt controller INTC, ROM controller, ROM and RAM blocks. It can be
output from the CLKOUT pin.
f
CPU
is the clock supplied to CPU.
Ring-OSC
X1
X2
PLL0 (
×
12)
PLL
PLL1 (
×
10)
f
XX
/32
f
XX
/16
f
XX
/8
f
XX
/4
f
XX
/2
f
XX
MPCCTL.STPPLL0
MPCCTL.STPPLL1
OCSK0
OCSK1
MPCCTL.MCKSEL
MPCCTL.PCKSEL
CKC.CKDIV0
CKC.CKDIV1
PSMR (IDLE2)
f
CPU
f
CLK
f
XX
f
X
f
R
PRS2
PRS1
Standby
control
Standby
control
Output
control
Output
control
Selector
Selector
Selector
Peripherals
WDT2
WDT2
1/8
PCC.CKm
t
PLL
_PCKSEL
t
PLL
_MCKSEL
t
PLL
_MCKSEL_CKDIV
OCKS2
PCLM.PCKm
PCLM.PCLE
CCLS.CCLSF
CPUCLK
SystemCLK
OCKS3
aFCAN, CSI3n
PLL
Extended clock for CSIBm
MPCCTL.SELPLL
PSMR (IDLE1)
PSMR (HALT)
BRGC
PCC.MFR
PSMR (STOP)
Main OSC
electronic components distributor