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Chapter 7
16-Bit Timer/Event Counter P
User’s Manual U16702EE3V2UD00
7.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011)
When TPnCE is set to 1 in the one-shot pulse mode, the 16-bit counter waits for the setting of the
TPnEST bit (to 1) or a trigger that is input when the edge of the TIPn0 pin is detected, while holding
FFFFH. When the trigger is input, the 16-bit counter starts counting up. When the value of the 16-bit
counter matches the value of the CCR1 buffer register that has been transferred from the TPnCCR1
register, TOPn1 goes high. When the value of the 16-bit counter
matches the value of the CCR0 buffer register that has been transferred from the TPnCCR0 register,
TOPn1 goes low, and the 16-bit counter is cleared to 0000H and stops. Input of a second or
subsequent trigger is ignored while the 16-bit counter is operating. Be sure to input a second trigger
while the 16-bit counter is stopped at 0000H. In the one shot pulse mode, rewriting the TPnCCR0 and
TPnCCR1 registers is enabled when TPnCE = 1. The set values of the TPnCCR0 and TPnCCR1
registers become valid after a write instruction from the CPU is executed. They are then transferred to
the CCR0 and CCR1 buffer registers, and compared with the value of the 16-bit counter. The waveform
of the one-shot pulse is output from the TOPn1 pin. The TOPn0 pin produces a toggle output when the
value of the 16-bit counter matches the value of the TPnCCR0 register. In the one-shot pulse mode, the
TPnCCR0 and TPnCCR1 registers function only as compare registers. They cannot be used as capture
registers.
Cautions: 1. In the one-shot pulse mode, select the internal clock (TPnEEE bit of TPnCTL1
register = 0) as the count clock.
2. In the one-shot pulse mode, it is prohibited to set the TPnCCR1 register to 0000H.
Remark:
n = 0 to 3
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