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User’s Manual U16702EE3V2UD00
Chapter 19
RESET Function
19.1 Overview
The following reset functions are available.
(1)
Five kinds of reset sources:
•
External reset input via the RESET pin
•
Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES)
•
System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected
voltage (see
Chapter 24
”Low-Voltage Detector” on page 781
)
•
System reset via the detecting clock monitor (CLM) oscillation stop (see
Chapter 25
”Clock
Monitor” on page 789
)
•
System reset by power-on clear circuit (POC) (see
Chapter 23
”Power-On-Clear Circuit” on
page 779
).
(2)
Emergency operation mode:
If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a
main clock oscillation anomaly is judged and the CPU starts operating on Ring-OSC.
Caution:
When the CPU is being operated via the Ring-OSC, access to the register in which a
wait state is generated is prohibited. For the register in which a wait state is gener-
ated, refer to 3.4.7 (3)”Accessing specific on-chip peripheral I/O registers” on
page 89.
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