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Chapter 13
3-Wire Serial Interface (CSIB)
User’s Manual U16702EE3V2UD00
13.7 Operation
13.7.1 Single transfer mode (master mode, transmission/reception mode)
Figure 13-9 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of
CBnCTL0 register = 0), when the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of
the CBnCTL1 register = 0, and when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the
CBnCTL2 register = 0, 0, 0, 0).
Figure 13-9:
Single Transfer Timing (Master Mode, Transmission/Reception Mode)
(1)
Clear the CBnPWR bit of the CBnCTL0 register.
(2)
Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3)
Specify the transfer mode by using the CBnDIR bit of the CBnCTL0 register and, at the same time,
enable transmission/reception by setting the CBnTXE, CBnRXE and CBnCSE bits of the
CBnCTL0 register to 1.
(4)
Enable CSIB operating clock supply by setting the CBnPWR bit of the CBnCTL0 register to 1.
(5)
Write transfer data to the CBnTX register (start transmission).
(6)
The reception complete interrupt request signal (INTCBnR) is generated to inform the CPU that
the CBnRX (CBnRXL) register can be read.
(7)
Read the CBnRX register before clearing the CBnPWR bit to 0.
(8)
Confirm that the CBnTSF bit of the CBnSTR register = 0, and stop clock supply to CSIB by clear-
ing the CBnPWR bit to 0 (end of transmission/reception).
To transfer more data, repeat (5) to (7) before (8).
Remark:
The processing in (3) and (4) can be set simultaneously.
CBnTX write (55H)
CBnRX read (AAH)
(AAH)
(55H)
1
0
1
1
0
1
55H (transmit data)
SCKBn
CBnTX
CBnRX
Shift
register
INTCBnR
SIBn
SOBn
0
0
0
1
0
0
1
0
1
1
(1) - (4)
(5)
(6)
(8)
(7)
AAH
00H
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
00H
CBnTSF
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