NEC V850E/RS1, User Manual, Page: 717 / 852

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Chapter 17 Interrupt/Exception Processing Function
User’s Manual U16702EE3V2UD00
17.5 Exception Trap
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes
place. Therefore, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an excep-
tion trap.
17.5.1 Illegal opcode definition
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to
1111B, and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable
to this illegal instruction is executed.
Figure 17-27: Illegal Opcode Definition
Remark:
×
: Arbitrary
Caution: Since it is possible to assign this instruction to an illegal opcode in the future, it is
recommended that it not be used.
(1) Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to
the handler routine.
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the NP, EP, and ID bits of the PSW.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and
transfers control.
Figure 17-28 illustrates the processing of the exception trap.
15 16 23 22
⋅ ⋅ ⋅ ⋅ ⋅ ⋅
0
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
1 1 1 1 1 1
⋅ ⋅ ⋅ ⋅ ⋅
27 26 31 0 4 5 10 11
1
1
1
1
1
1
0
1
to
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