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Chapter 3
CPU Function
User’s Manual U16702EE3V2UD00
(3)
Internal peripheral I/O area
4 KB of addresses 3FFF000H to 3FFFFFFH are allocated as the internal peripheral I/O area.
Figure 3-22:
Internal Peripheral I/O Area
Peripheral I/O registers that have functions to specify the operation mode for and monitor the sta-
tus of the internal peripheral I/O are mapped to the internal peripheral I/O area. Program cannot
be fetched from this area.
Cautions: 1. When a register is accessed in word units, a word area is accessed twice in half-
word units in the order of lower area and higher area, with the lower 2 bits of the
address ignored.
2. If a register that can be accessed in byte units is accessed in half word units, the
higher 8 bits are undefined when the register is read, and data is written to the
lower 8 bits.
3. Addresses not defined as registers are reserved for future expansion. The opera-
tion is undefined and not guaranteed when these addresses are accessed.
Internal peripheral I/O area
(4 KB)
3FF FFFFH
3FF F000H
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