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Chapter 9
16-Bit Interval Timer M
User’s Manual U16702EE3V2UD00
9.2 Configuration
TMM0 includes the following hardware.
Figure 9-1:
Block Diagram of TMM0
Remark:
f
XX
: Internal system clock frequency
f
R
: Ring-OSC clock frequency
(1)
TMM0 compare register 0 (TM0CMP0)
The TM0CMP0 register is a 16-bit compare register.
This register can be read or written in 16-bit units.
RESET input clears this register to 0000H.
The same value can always be written to the TM0CMP0 register by software.
Rewriting the TM0CMP0 register is prohibited when the TM0CE bit = 1.
Figure 9-2:
TMM0 Compare Register 0 (TMnCMP0) Format
Table 9-1:
Configuration of TMM
Item
Configuration
Timer register
16-bit counter
Register
TMM0 compare register 0 (TM0CMP0)
Control register
TMM0 timer control register (TM0CTL0)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
R/W
Initial
value
TM0CMP0
FFFF F694H
R/W 0000H
TM0CTL0
Internal bus
f
XX
f
XX
/2
f
XX
/4
f
XX
/64
f
XX
/512
f
XX
/32
f
XX
/8
f
RING
Controller
16-bit counter
Match
Clear
INTTM0EQ0
TM0CMP0
TM0CE TM0CKS2 TM0CKS1TM0CKS0
Selector
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