
428
Chapter 12
Asynchronous Serial Interface A (UARTA)
User’s Manual U16702EE3V2UD00
(7)
Permissible baud rate range for reception
The permissible baud rate error during reception is shown below.
Caution:
Be sure to set the baud rate error for reception to within the permissible error range,
by using the expressions shown below.
Figure 12-17:
Permissible Baud Rate Range for Reception
After the start bit is detected, the counter set by the UAnCTL2 register determines the latch timing
of the receive data, as shown in Figure 12-17. If the last data (stop bit) is received at this latch tim-
ing, the data can be correctly received.
Assuming 11 bits of data are to be received, the theoretical baud rate is as follows.
FL = (Brate) – 1
Brate: Baud rate of UARTAn (n = 0 to 1)
k:
Set value of UAnCTL2 (n = 0 to 1)
FL:
1-bit data length
Margin of latch timing: 2 clocks
Permissible minimum transfer rate:
FL
1 data frame (11
×
FL)
FLmin
FLmax
Transfer rate
of UARTAn
Bit 0
Start bit
Bit 1
Bit 7
Parity bit
Permissible
minimum
transfer rate
Permissible
maximum
transfer rate
Bit 0
Start bit
Bit 1
Bit 7
Parity bit
Latch
timing
Bit 0
Start bit
Bit 1
Bit 7
Parity bit
Stop bit
Stop bit
Stop bit
Flmin = 11
×
FL –
×
FL = FL
2k
k - 2
2k
21k + 2
electronic components distributor