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Chapter 14
Queued CSI (CSI30, CSI31)
User’s Manual U16702EE3V2UD00
Figure 14-2:
Queued CSI Operation Mode Registers (CSIM0, CSIM1) Format (2/2)
Caution:
Write is permitted only when CTXE = 0 and CRXE = 0.
See section
14.3.2 ”Serial Data Direction Select Function” on page 477
for further details on
the DIR bit setting.
Caution:
Write is permitted only when CTXE = 0 and CRXE = 0.
This bit is only valid in master mode. In slave mode, no delay is generated.
Caution:
Write is permitted only when CTXE = 0 and CRXE = 0.
This bit is only valid in master mode. In slave mode, no wait is generated.
Caution:
Write is permitted only when CTXE = 0 and CRXE= 0.
This bit is only valid for CSWE=1.
This bit is only valid in master mode. In slave mode, CS signals are always held at
inactive level.
In combination:
See section
14.3.10 ”Additional Timing and Delay Selections” on page 486
for further details
on the timing selections by CSIT, CSWE, CSMD bits.
DIR
Serial data direction selection
0
Data is sent/received with MSB first
1
Data is sent/received with LSB first
CSIT
Interrupt delay mode select (INTC3nI signal)
0
No delay
1
Half clock delay
CSWE
Transmission wait enable/disable select
0
Transmission wait disable. Not insert 1 clock (SCK3) wait at transmission start.
1
Transmission wait enable. Insert 1 clock (SCK3) wait at transmission start.
CSMD
Chip Select mode select
0
Chip select inactive level output disable. Do not force chip select inactive state after each
transfer of a data element.
1
Chip select inactive level output enable. Hold all chip selects inactive for halt-length SCK3
after each transfer of a data element.
CSWE
CSMD
Transmission wait
Chip Select inactive level
0
0
None
Not output
0
1
None
Not output
1
0
One SCK3 length clock wait
Not output
1
1
One SCK3 length clock wait
Output inactive level of half-length SCK3
during first half of transmission wait
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