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Chapter 5
Bus Control Function
User’s Manual U16702EE3V2UD00
5.7.2 Bus hold procedure
The bus hold status transition procedure is shown below.
Figure 5-8:
Bus Hold Status Transition Procedure
5.7.3 Operation in power save mode
Because the internal system clock is stopped in the software STOP and IDLE modes, the bus hold
status is not entered even if the HLDRQ pin is asserted.
In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the
bus hold status is entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also
deasserted, and the bus hold status is cleared.
<1>
¯¯¯¯¯¯¯
HLDRQ = 0 acknowledged
<2> All bus cycle start requests inhibited
<3> End of current bus cycle
<4> Shift to bus idle status
Normal status
<5>
¯¯¯¯¯¯
HLDAK = 0
<6>
¯¯¯¯¯¯¯
HLDRQ = 1 acknowledged
Bus hold status
<7>
¯¯¯¯¯¯
HLDAK = 1
<8> Bus cycle start request inhibition released
<9> Bus cycle starts
Normal status
HLDAK (output)
HLDRQ (input)
<1> <2>
<5>
<3><4>
<7><8><9>
<6>
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