789
User’s Manual U16702EE3V2UD00
Chapter 25
Clock Monitor
25.1 Functions of Clock Monitor
The clock monitor samples the main clock (X1 input clock) by using the on-chip Ring-OSC, and
generates a reset request signal when oscillation of the main clock is stopped.
Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be
cleared to 0 by any means other than reset.
The clock monitor automatically stops under the following conditions.
•
While oscillation stabilization time is being counted after software STOP mode is released
•
When the main clock (X1 input clock) is stopped
•
When the sampling clock is stopped (Ring-OSC)
•
When the CPU operates with Ring-OSC
25.2 Configuration of Clock Monitor
Clock monitor consists of the following hardware.
Figure 25-1:
Block Diagram of Clock Monitor
Table 25-1:
Configuration of Clock Monitor
Item
Configuration
Control register
Clock monitor mode register (CLM)
X1 input clock
Ring-OSC clock
Internal reset signal
Enable/disable
CLME
Clock monitor mode register (CLM)
electronic components distributor