64
Chapter 3
CPU Function
User’s Manual U16702EE3V2UD00
3.2.2 System
register
set
System registers control the status of the CPU and hold interrupt information.
Read from and write to system registers are performed by setting the system register numbers shown
below with the system register load/store instructions (LDSR, STSR instructions).
Notes: 1.
Since only one set of these registers is available, the program must save the contents of
these registers when multiple interrupt servicing is permitted.
2.
Since only one set of these registers is available, the program must save the contents of
these registers when CALLT instructions nesting are used.
3.
These registers can be accessed only when the DBTRAP instruction is executed.
Caution:
Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is
ignored when execution is returned to the main routine by the RETI instruction after
interrupt servicing (this is because bit 0 of the PC is fixed to 0). Set an even value to
EIPC, FEPC, and CTPC (bit 0 = 0).
Remark:
√
: Can be accessed
×
: Access prohibited
Table 3-2:
System Register Numbers
Register
Number
System Register Name
Operand Specification
LDSR
Instruction
STSR
Instruction
0
Interrupt status saving register (EIPC)
√
Note 1
√
1
Interrupt status saving register (EIPSW)
√
Note 1
√
2
NMI status saving register (FEPC)
√
√
3
NMI status saving register (FEPSW)
√
√
4
Interrupt source register (ECR)
×
√
5
Program status word (PSW)
√
√
6 to 15
Reserved for future function expansion (operation is not guaranteed if
these registers are accessed)
×
×
16
CALLT execution status saving register (CTPC)
√
Note 2
√
17
CALLT execution status saving register (CTPSW)
√
Note 2
√
18
Exception/debug trap status saving register (DBPC)
√
Note 3
√
19
Exception/debug trap status saving register (DBPSW)
√
Note 3
√
20
CALLT base pointer (CTBP)
√
√
21 to 31
Reserved for future function expansion (operation is not guaranteed if
these registers are accessed)
×
×
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