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Chapter 14
Queued CSI (CSI30, CSI31)
User’s Manual U16702EE3V2UD00
(9)
FIFO Buffer Transfer Mode (Master Mode, Transmit/Receive Mode)
MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS
inactive disabled (CSMD = 0), CKP = 1, DAP = 0, transmission data length of 8 bits
(CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”:
Figure 14-33:
FIFO Buffer Transfer Mode (Master, Transmit/Receive) Timing
1.
Set the CSIM register's POWER bit to 1 to enable the supply of the Queued CSI operation clock.
2.
Set the CSIC and CSIL registers to specify the transfer mode.
3.
Write “1” in the SFA register's FPCLR bit to clear all FIFO pointers.
4.
Specify the transfer mode using the CSIM register's TRMD, DIR, and CSIT bits; at the same time,
set the CTXE and CRXE bits to 1 to enable the transmit/receive operation.
5.
Set the number of transmit/receive data items in the SFN register's SFN[3:0] bits.
6.
Make sure that the SFA register's SFFUL bit is set to 0, then write chip-select data and
transmission data in the SFCS and SFDB registers in this order.
7.
Wait for the transmissions/receptions to be completed (e.g. by monitoring the INT3C3nI interrupt).
8.
Read the received data by multiple read of the SIRB register (= sequential read from the FIFO).
9.
Write “1” in the SFA register's FPCLR bit and clear all FIFO pointers for the next transmission.
To continue transmission/reception, repeat steps (5) - (9).
10. Set the CSIM register's CTXE and CRXE bits to 0 to disable the transmit/receive operation (end of
transmit/receive operation).
CTXE, CRXE
SFDB write
CSIBUF-empty
CSIBUF_0
CSIBUF_1
CSIBUF_2
SCK3
SI3
SO3
SIRB read
INTC3nI
(1)
CS3n[3:0]
CSOT
3H
"active-L"
33H
CS 2
CS 1
CS 0
2H
0H
1H
1
1
1
1
1
1
1
1
1 1
1
1
1
1 1
1
1 1
1
1 1
1
0
0
0
0
0
0
0 0
0
0
0 0
0
0 0
0
0
0
0 0
Wait insertion
by CSIBUF-empty
SFP3-0
SFN3-0
(2)(3)
(4)
(5)
(6)
(6)
(9)
(10)
(8)
(8)
(7)
55H
AAH
96H
CCH
0
0 0
0
1
1
(6)
(8)
99H
0H
3H
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