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Chapter 8
16-Bit Timer/Event Counter Q
User’s Manual U16702EE3V2UD00
8.4 Control
Registers
(1)
Timer Q0 control register 0 (TQnCTL0)
Timer Q0 control register 0 is an 8-bit register that controls the operation of timer Q.
This register can be read and written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
The same value can always be written to the TQnCTL0 register by software.
Figure 8-7:
Timer Qn Control Register 0 (TQnCTL0) Format
Caution:
Set bits TQnCKS2 to TQnCKS0 when TQnCE = 0.
When the value of the TQnCE bit is changed from 0 to 1, bits TQnCKS2 to TQnCKS0
can be set simultaneously.
Remark:
n = 0, 1
Symbol
<7>
6
5
4
3
2
1
0
Address
R/W
After
reset
TQ0CTL0 TQ0CE
0
0
0
0
TQ0CKS2 TQ0CKS1 TQ0CKS0 FFFFF540H R/W 00H
Symbol
<7>
6
5
4
3
2
1
0
Address
R/W
After
reset
TQ1CTL0 TQ1CE
0
0
0
0
TQ1CKS2 TQ1CKS1 TQ1CKS0 FFFFF610H R/W 00H
TQnCE
Timer Qn operation control
0
Disable internal operating clock operation (asynchronously reset TMQn).
1
Enable internal operating clock operation.
The TQnCE bit controls the internal operating clock and asynchronously resets TMQn. When this bit is
cleared to 0, the internal operating clock of TMQn is stopped (fixed to the low level), and TMQn is
asynchronously reset.
When the TQnCE bit is set to 1, the internal operating clock is enabled within 2 input clocks, and TMQn
counts up.
TQnCKS2
TQnCKS1
TQnCKS0
Internal count clock selection
0
0
0
f
XX
0
0
1
f
XX
/2
0
1
0
f
XX
/4
0
1
1
f
XX
/8
1
0
0
f
XX
/16
1
0
1
f
XX
/32
1
1
0
f
XX
/64
1
1
1
f
XX
/128
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