NEC V850E/RS1, User Manual, Page: 735 / 852

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Chapter 18 Standby Function
User’s Manual U16702EE3V2UD00
(2) Releasing STOP mode by RESET pin input
The same operation as the normal reset operation is performed.
Table 18-8: Operation After Releasing STOP Mode by Interrupt Request
Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status
Non-maskable interrupt
request
Execution branches to the handler address after securing the prescribed setup time.
Maskable interrupt
request
Execution branches to the handler
address or the next instruction is
executed after securing the prescribed
setup time
The next instruction is executed after
securing the prescribed setup time.
Table 18-9: Operation Status in STOP Mode
Setting of STOP Mode
Operation Status
Item
Main clock oscillator (f
X
)
Stops operation
Ring clock generator (f
R
)
Oscillation enabled
PLL Stops operation
Flash charge pump Stops operation
CPU Stops operation
DMA Stops operation
Interrupt controller Stops operation (Standby mode release enabled)
Timer P (TMP0 to TMP3) Stops operation
Timer Q (TMQ0, TMQ1) Stops operation
Timer M (TMM0)
Operable when f
R
/8 is selected as the count clock
Watchdog timer 2 (WDT2)
Operable when f
R
is selected as the count clock
Serial
interface
CSIB0, CSIB1 Operable when SCKB0, SCKB1 input clock is selected as operation clock
UARTA0, UARTA1
Stops operation (Operable when ASCKA0 input clock is selected as
operation clock)
CSI30, CSI31 Stops operation
AFCAN0, AFCAN1 Stops operation
A/D converter Stops operation
External bus interface Refer to CHAPTER 5 BUS CONTROL FUNCTION .
Port function Retains status before STOP mode was set.
Internal data
The CPU registers, statuses, data, and all other internal data such as the
contents of the internal RAM are retained as they were before the STOP
mode was set.
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