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Chapter 5
Bus Control Function
User’s Manual U16702EE3V2UD00
5.5 Wait
Function
5.5.1 Programmable wait function
(1)
Data wait control register 0 (DWC0)
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted
in the bus cycle that is executed for each CS space.
The number of wait states can be programmed for each chip select area (CS0, CS1) by using data
wait control register 0 (DWC0). Immediately after system reset, 7 data wait states are inserted for
all the blocks.
The DWC0 register can be read or written in 16-bit units.
Cautions: 1. The internal ROM and internal RAM areas are not subject to programmable wait,
and are always accessed without a wait state. The on-chip peripheral I/O area is
also not subject to programmable wait, and only wait control from each
peripheral function is performed.
2. Write to the DWC0 register after reset, and then do not change the set values.
Also, do not access an external memory area other than the one for this
initialization routine until the initial settings of the DWC0 register are complete.
However, external memory areas whose initial settings are complete may be
accessed.
Figure 5-4:
Data Wait Control Register 0 (DWC0) Format
Caution:
Be sure to set to 1 bits 14 to 12 and bits 10 to 8.
Be sure to clear to 0 bits 15, 11, 7, and 3.
Symbol
15
14
13
12
11
10
9
8
Address
After reset
DWC0
0
1
1
1
0
1
1
1
FFFFF484H
7777H
R/W
7
6
5
4
3
2
1
0
0
DW12
DW11
DW10
0
DW02
DW01
DW00
I________________I
I________________I
CSn
signal
CS1
CS0
DWn2
DWn1
DWn0
Number of wait states inserted in memory block n space
(n = 0, 1)
0
0
0
None
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
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