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Chapter 10
Functions of Watchdog Timer 2
User’s Manual U16702EE3V2UD00
10.4 Operation
(1)
Oscillation stabilization time selection function
The wait time until the oscillation stabilizes after the software STOP mode is released is controlled
by the OSTS register.
The OSTS register can be read or written 8-bit units.
RESET input sets this register to 03H.
Figure 10-5:
Oscillation Stabilization Time Selection Function
Note:
The oscillation stabilization time and setup time are required when the software stop mode and
idle mode are released, respectively.
Cautions: 1. The wait time following release of the software STOP mode does not include the
time until the clock oscillation starts (“a” in the figure below) following release of
the software STOP mode, regardless of whether the software STOP mode is
released by RESET input or the occurrence of an interrupt request signal.
2. Be sure to clear bits 3 to 7 to 0.
3. The oscillation stabilization time following reset release is 2
13
/f
X
(because the
initial value of the OSTS register = 03H).
Remark:
f
X
= Main clock oscillator frequency
Symbol
7
6
5
4
3
2
1
0
Address
After reset
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
FFFFF6C0H
03H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OSTS2
OSTS1
OSTS0
Selection of oscillation stabilization time/setup time
Note
f
X
Selected clock
8 MHz
0
0
0
2
10
/f
X
0.128 ms
0
0
1
2
11
/f
X
0.256 ms
0
1
0
2
12
/f
X
0.512 ms
0
1
1
2
13
/f
X
1.024 ms
1
0
0
2
14
/f
X
2.048 ms
1
0
1
2
15
/f
X
4.096 ms
1
1
0
2
16
/f
X
8.192 ms
1
1
1
Setting prohibited
a
STOP mode release
Voltage waveform of X1 pin
V
SS
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