36
Chapter 1
Introduction
User’s Manual U16702EE3V2UD00
1.6.2 On-chip
units
(1)
CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits
×
16 bits
→
32 bits or 32 bits
×
32 bits
→
64 bits), barrel shifter (32-bit), and other dedicated hardware are on-chip to accelerate
complex instruction processing.
(2)
Bus control unit (BCU)
The BCU starts a required external bus cycle based on a physical address obtained from the CPU.
If there is no bus cycle start request from the CPU when fetching an instruction from an external
memory area, the BCU generates a prefetch address and prefetches the instruction code. The
prefetched instruction code is fetched into the internal instruction queue of the CPU.
(3)
Memory controller (MEMC)
The MEMC controls SRAM, ROM, and various I/O for external memory expansion.
(4)
DMA controller (DMAC)
A 6-channel DMA controller is provided on chip. This controller transfers data between the internal
RAM and on-chip peripheral I/O devices in response to interrupt requests sent by on-chip periph-
eral I/O.
(5)
ROM
The µPD70F3402 has an on-chip flash memory of 128 Kbytes.
The µPD70F3403 and µPD70F3403A have an on-chip flash memory of 256 Kbytes.
The 128 KB or 256 KB flash memory are mapped to the address spaces from 0000000H to
001FFFFH, or 0000000H to 003FFFFH, respectively.
During instruction fetch, flash memory can be accessed from the CPU in 1-clock cycle.
(6)
RAM
This consists of a 10 KB or 16 KB RAM mapped to the address spaces from 3FFC800H to
3FFEFFFH or 3FFB000H to 3FFEFFFH, respectively.
During instruction fetch or data access RAM memory can be accessed from the CPU in 1-clock
cycle.
(7)
Interrupt controller (INTC)
The INTC services hardware interrupts requests from on-chip peripheral I/O and external sources.
Eight levels of interrupt priorities can be specified for this interrupt requests, and multiprocessing
controls against the interrupt sources can be performed.
(8)
Clock generator (CG)
This clock generator supplies frequencies for the CPU and the built-in peripherals. As the input
clock, an external oscillator is connected to pins X1 and X2.
The clock generator has 2 PLL which could be independently assigned either to the peripherals or
to the CPU. It generates seven types of clocks (f
XX
, f
XX
/2, f
XX
/4, f
XX
/8, f
XX
/16, f
XX
/32, f
ring
), and
supplies one of them as the operating clock for the CPU (f
CPU
).
(9)
Ring-OSC
A Ring-OSC is provided on chip. The oscillation frequency is 220 kHz (TYP.). This Ring-OSC sup-
plies the clock for the watchdog timer 2 and timer TMM.
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