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Chapter 12
Asynchronous Serial Interface A (UARTA)
User’s Manual U16702EE3V2UD00
12.5.7 Noise filter of receive data
The RXDAn pin is sampled using the UART internal clock (f
XCLK
).
If the sampled value is the same twice in a row, the output of the match detector changes, and the sig-
nal on the RXDAn pin is sampled as input data.
Because the circuit configuration of the noise filter is as shown in Figure 12-15, internal processing of a
reception operation is delayed two clocks from the external signal status.
Figure 12-15:
Noise Filter Circuit
fxclk
(internal UART clock)
RXDAn
Internal signal A
Internal signal B
Internal signal C
Match
detector
LD_EN
In
In
In
Q
Q
Q
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