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Chapter 7
16-Bit Timer/Event Counter P
User’s Manual U16702EE3V2UD00
7.4 Control
Registers
(1)
TMPn control register 0 (TPnCTL0)
TMPn control register 0 is an 8-bit register that controls the operation of timer P.
This register can be read and written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
The same value can always be written to the TPnCTL0 register by software.
Figure 7-5:
TMPn Control Register 0 (TPnCTL0) Format
Caution:
Set bits TPnCKS2 to TPnCKS0 only when TPnCE = 0.
When TPnCE bit setting is changed from 0 to 1, TPnCKS2 to TPnCKS0 bits can be set
simultaneously.
Remark:
n = 0 to 3
f
RING
: Ring oscillator frequency
Address: TP0CTL0: FFFFF590H, TP1CTL0: FFFFF5A0H
TP2CTL0: FFFFF5B0H, TP3CTL0: FFFFF5C0H
Symbol
7
6
5
4
3
2
1
0
Address
R/W
After
reset
TPnCTL0
TPnCE
0
0
0
0
TPnCKS2 TPnCKS1 TPnCKS0
FFFFF590H
to
FFFFF5C0H
R/W 00H
TPnCE
Timer Pn operation control
0
Disable internal operating clock operation (TMPn is asynchronously reseted)
1
Enable internal operating clock operation
Internal operating clock control and TMPn asynchronous reset are performed with the TPnCE bit. When
TPnCE bit is cleared to 0, the internal operating clock of TMPn stops (fixed to low level) and TMPn is reset
asynchronously.
When the TPnCE bit is set to 1, the internal operating clock is enabled within 2 input clocks, and TMPn
counts up.
TPnCKS2
TPnCKS1
TPnCKS0
Internal count clock selection
n = 0, 2
n = 1, 3
0
0
0
f
XX
0
0
1
f
XX
/2
0
1
0
f
XX
/4
0
1
1
f
XX
/8
1
0
0
f
XX
/16
1
0
1
f
XX
/32
1
1
0
f
XX
/64
1
1
1
f
XX
/128
f
RING
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