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Chapter 8
16-Bit Timer/Event Counter Q
User’s Manual U16702EE3V2UD00
(6)
Timer Q option register 0 (TQnOPT0)
The TQnOPT0 register is an 8-bit register that selects a capture or compare operation, and
detects an overflow.
This register can be read and written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
Figure 8-12:
Timer Q Option Register 0 (TQnOPT0) Format
Cautions: 1. Rewrite bits TQnCCS3 to TQnCCS0 when TQnCE = 0. (The same value can be
written when TQnCE = 1.) If rewriting was mistakenly performed, set TQnCE = 0
and then set the bits again.
2. Be sure to clear bits 1, 2 and 3 to 0.
Remark:
n = 0, 1
m = 0 to 3
Symbol
7
6
5
4
3
2
1
<0>
Address
R/W
After
reset
TQ0OPT0 TQ0CCS3 TQ0CCS2 TQ0CCS1 TQ0CCS0
0
0
0
TQ0OVF
FFFFF545H R/W 00H
Symbol
7
6
5
4
3
2
1
<0>
Address
R/W
After
reset
TQ1OPT0 TQ1CCS3 TQ1CCS2 TQ1CCS1 TQ1CCS0
0
0
0
TQ1OVF
FFFFF615H R/W 00H
TQnCCSm
Selection of capture or compare operation of TQnCCRm register
0
Compare register
1
Capture register
The TQnCCSm bit setting is valid only in the free-running mode.
TQnOVF
Detection of Timer Q overflow
Set (1)
Overflow occurrence
Reset (0)
0 written to TQnOVF bit or TQnCE = 0
•
The TQnOVF bit is reset when the 16-bit counter value overflows from FFFFH to 0000H in the free-
running mode or the pulse width measurement mode.
•
As soon as the TQnOVF bit has been set to 1, an interrupt request signal (INTTQnOV) is generated.
The INTTQnOV signal is not generated in any mode other than the free-running mode and pulse width
measurement mode.
•
The TQnOVF bit is not cleared even when the TQnOVF bit and the TQnOPT0 register are read when
TQnOVF = 1.
•
The TQnOVF bit can be both read and written, but 1 cannot be written to the TQnOVF bit from the
CPU. Writing 1 has no influence on the operation of timer Q.
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