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Chapter 15
DMA Functions (DMA Controller)
User’s Manual U16702EE3V2UD00
Figure 15-10:
DMA Channel Control Register (DMCHCn) Format (4/4)
Caution:
Write to FCLR = 1 is permitted only when EN = 0 (DMCHCn register).
Remarks: 1.
This bit is a trigger bit only. When reading the bit, the read value is always 0.
2.
The RQST flag is cleared two clock cycles after setting FCLR = 1.
Caution:
Do not set FCLR and STG bits at the same time. If set at the same time, FCLR gets
priority.
Remark:
This bit is a trigger bit only. When reading the bit, the read value is always 0.
FCLR
DMA Request Clear Trigger
0
No change
1
Clear any pending DMA transfer request.
STG
DMA Software Trigger
0
No change
1
Generate a DMA transfer trigger.
EN
DMA Transfer Enable
0
DMA transfer is disabled or the total number of DMA transfers is finished.
If EN set to 0 while a “Single” or “Fixed Channel” transfer is active, the DMA transfer is stopped
(the DMA source address, destination address, and transfer count registers are held.). When EN
is set to 1 again, the DMA transfer is re-started.
1
DMA transfer is enabled and/or the total number of DMA transfers is not finished.
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