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Chapter 8
16-Bit Timer/Event Counter Q
User’s Manual U16702EE3V2UD00
8.5.5 One-shot pulse mode (TQnMD2 to TQnMD0 = 011)
When TQnCE is set to 1 in the one-shot pulse mode, the 16-bit counter waits for the setting of the
TQnEST bit (to 1) or a trigger that is input when the edge of the TIQn0 pin is detected, while holding
FFFFH. When the trigger is input, the 16-bit counter starts counting up. When the value of the 16-bit
counter matches the value of the CCRk buffer register that has been transferred from the TQnCCR0
register, TOQnk goes high. When the value of the 16-bit counter matches the value of the CCR0 buffer
register that has been transferred from the TQnCCR0 register, TOQnk goes low, and the 16-bit counter
is cleared to 0000H and stops. Input of a second or subsequent trigger is ignored while the 16-bit
counter is operating. Be sure to input a second trigger while the 16-bit counter is stopped at 0000H.
In the one-shot pulse mode, rewriting the TQnCCRm register is enabled when TQnCE = 1. The set
value of the TQnCCRm register becomes valid after a write instruction from the CPU is executed. They
are then transferred to the CCRm buffer register, and compared with the value of the 16-bit counter.
The waveform of the one-shot pulse is output from the TOQnk pin. The TOQnm pin produces a toggle
output when the value of the 16-bit counter matches the value of the TQnCCR0 register.
In the one-shot pulse mode, the TQnCCRm register function only as a compare register. It cannot be
used as a capture register.
Caution:
In the one-shot pulse mode, select the internal clock (TQnEEE bit of TQnCTL1
register = 0) for the count clock.
Remark:
n = 0 to 1
m = 0 to 3
k = 1 to 3
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