Digital Equipment DECstation 5000/100 Series, Maintenance Manual

Page: 384 / 392

System Interrupt Mask Register
Table E-11. System Interrupt Mask Register 0x1C040120
Bits Access Description
31:0 R/W Interrupt mask
<31:0>
These bits, if 0, mask the corresponding interrupt observable in
the SIR. Bit <0> masks SIR<0>, bit <1> masks SIR<1>, and so
on. The mask does not prevent an interrupt from showing up in
the SIR; it merely keeps the CPU from being interrupted. The
interrupt mask is set to 0’s on power up, masking all interrupts.
Software must set to 1 those interrupts that it wants enabled.
E–28 CPU and System Registers