Digital Equipment DECstation 5000/100 Series, Maintenance Manual

Page: 377 / 392

System Interrupt Register (SIR)
The SIR interrupt register consists of two sections. Bits
<31:16> are set by the DMA engine for sundry DMA conditions.
These bits are always set by the system and can be cleared
by writing 0 to them. Writing 1 has no effect. These bits are
cleared to 0 during system power up or reset.
Bits <15:0> reflect the status of specific system devices and are
read only. A few of these are not usually used as interrupts
and should be masked. These bits may or may not be reset to
0 during system power up reset, depending on the state of the
interrupting device.
CPU and System Registers E–21