Digital Equipment DECstation 5000/100 Series, Maintenance Manual

Page: 366 / 392

the IsC bit is set, store operations affect only the cache (main
memory writes are inhibited), and load operations return the
data at the addressed location in the cache, whether a cache
miss occurs (main memory reads are inhibited). Uncached data
references are not generally useful with IsC set. Uncached
store operations affect neither the cache nor the main memory
system, and uncached load operations return the data at the
addressed location in the cache. IsC affects only data reference;
instruction fetches are not affected. This bit can also be used
by operating system code to flush caches without causing
associated main memory accesses.
The PZ bit, when set, causes zero to replace the normal
outgoing parity bits that are generated on a store instruction,
covering both cache data and tags. This permits the writing
of incorrect parity bits in the caches and the checking of each
parity tree individually within the cache diagnostics.
The CM bit, when the cache is isolated, indicates whether the
most recent data cache load resulted in a cache miss. This bit
is used by cache test programs to verify the proper functioning
of the cache tag and parity bits.
The PE bit indicates whether a cache parity error occurred. It
is set on a cache parity error and reset by writing 1 to this bit.
Writing a zero to this bit does not affect its value. This bit is
used to log cache parity errors in software; otherwise, recovery
from them is completely transparent. Within cache diagnostics,
the PE bit is used to verify proper functioning of the cache
parity bits and the cache parity trees.
The TS bit is read only and indicates that the TLB has shut
down due to attempts to access several entries in the TLB
simultaneously. This mechanism protects the TLB from
hardware failures in the event of catastrophic software misuse
of the TLB. When the TLB is in this state, all translations and
PROBE accesses are inhibited and have undefined effects. This
state can be cleared only by a reset operation.
The bootstrap exception vectors (BEV) bit, when set, relocates
the UTLB miss exception vector to an address of 0xbfc00100
and the general exception vector to 0xbfc00180 (general),
respectively.
E–10 CPU and System Registers