Digital Equipment DECstation 5000/100 Series, Maintenance Manual

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SSR<31>
When set to 1, this bit enables communication port 1 (serial line 2)
to transmit DMA to SCC(0)-B. Communication port 1 is the
right comm port, viewed from the back.
SSR<30>
When set to 1, this bit enables communication port 1 (serial line 2)
to receive DMA from SCC(0)-B. Communication port 1 is the
right comm port, viewed from the back.
SSR<29>
When set to 1, this bit enables communication port 2 (serial line
3) to transmit DMA to SCC(1)-B. Communication port 2 is the
left comm port, viewed from the back.
SSR<28>
When set to 1, this bit enables communication port 2 (serial line
3) to receive DMA from SCC(1)-B. Communication port 2 is the
left comm port, viewed from the back.
SSR<27:19>
These bits are reserved.
SSR<18>
This bit, set to 0 on power up or reset, determines the direction
of the SCSI DMA transfer. If the bit is 0, then memory data
will be supplied to the 53C94 SCSI controller upon demand
from the address specified by the SCSI DMA pointer. If the bit
is set to 1, data bursts of two words supplied from the 53C94
SCSI controller are written to memory.
SSR<17>
When set to 1, this bit enables SCSI DMA; 0 disables it.
SSR<16>
When set to 1, this bit enables LANCE DMA so that the
Ethernet interface can begin data transfer.
SSR<15> DIAGDN
This bit reflects the state of the DIAGDN pin on the mother-
board, which is used by manufacturing diagnostics.
E–18 CPU and System Registers