Digital Equipment DECstation 5000/100 Series, Maintenance Manual

Page: 381 / 392

SIR<18>
This bit is set when the buffer pointer is not reloaded soon
enough. It indicates an overrun condition as the data buffer
space is exhausted. DMA is disabled when this bit is set. Clear
this bit by writing 0 to it.
SIR<17>
This bit is set when the SCSI DMA encounters a memory read
error during a DMA. DMA is disabled when this bit is set.
Clear this bit by writing 0 to it.
SIR<16>
This bit is set to 1 when the LANCE DMA encounters a
memory read error, disabling DMA. The LANCE will then
enter a timeout state, interrupting the processor to handle the
problem. The address of the error will be visible in the LPR.
Clear this bit by writing 0 to it; writing 1 to it has no effect.
SIR<15>
This bit is reserved.
SIR<14> UNSCUR
When this bit is set, the contents of the NV RAM in the TOY
clock chip are set to default system values. Any password that
had been saved is lost.
SIR<13>
This bit is reserved.
SIR<12> processor I/O write timeout
This interrupt is generated by the processor when an I/O write
fails to respond within the timeout period. The error address
should be logged in the error address register in the processor.
See the processor specifications for more information.
SIR<11>
This bit is reserved.
CPU and System Registers E–25