Digital Equipment DECstation 5000/100 Series, Maintenance Manual

Page: 73 / 392

CACHE MISS SET
CACHE PARITY ERROR SET
TLB SHUTDOWN SET
BOOTSTRAP EXCEPTION VECTOR SET
BAD VIRT ADR x10000000
SP xFFFFDDA8
SSR x50070F00
LANCE DMA DISABLE
SCSI DMA ENABLE
SCSI DMA WRITE TO MEMORY
COMM PORT 2 RECEIVE DMA DISABLE
COMM PORT 2 TRANSMIT DMA ENABLE
COMM PORT 1 RECEIVE DMA DISABLE
COMM PORT 1 TRANSMIT DMA ENABLE
SIR x00001002
CPU I/O - WRITE TIMEOUT
SIRM x0000F204
SCSI INTERRUPT FROM 53C94 ENABLED
Analysis of Example 1
The following list describes the useful
information in ENTRY 2 and ENTRY 3.
ENTRY 2 records the error.
The OS EVENT TYPE field indicates the PANIC type.
The PANIC MESSAGE field indicates that the error is
a CPU write timeout.
ENTRY 3 records the error and status register values at
the time of the CPU write timeout error.
The CAUSE register has no information because the
write timeout is an interrupt.
The BAD VIRT ADR register identifies the address of
the timeout.
The SIR register indicates that the system interrupt
was a CPU I/O write timeout.
Troubleshooting Tools 3–17