Digital Equipment DECstation 5000/100 Series, Maintenance Manual

Page: 379 / 392

Table E-10 (Cont.). System Interrupt Register 0x1C040110
Bits Access Description
2 R SCSI data ready
1 R PBNC
0 R PBNO
Note:
Communication port 1 is the same as serial line 2.
Communication port 2 is the same as serial line 3.
SIR<31>
This interrupt is generated by the communication port 1
transmit DMA logic. The DMA transmitter, when enabled,
transmits bytes until the pointer reaches a 4-Kbyte page
boundary. At this point it stops DMA and interrupts the
processor. DMA is disabled whenever this bit is set. To restart,
clear this bit by writing 0; writing 1 has no effect.
SIR<30>
When a parity error, page crossing error, or maximum transfer
length error occurs during a communication transmit port 1
DMA, this bit is set and the DMA is disabled. The DMA pointer
contains the error address. Check the memory sections for more
information. To restart, software must clear this bit by writing
0; writing 1 has no effect.
SIR<29>
When the receive DMA pointer associated with communication
port 1 reaches a half page (2-Kbyte) boundary, this bit is set.
Software must disable DMA and then load a new pointer
and restart DMA without being interrupted. Clear this bit
by writing 0; writing 1 has no effect. The value of this bit is
informational only and does not stop the DMA.
SIR<28>
When the receive DMA pointer associated with communication
port 1 reaches a page boundary, this bit is set and the DMA
disabled. To restart, clear this bit by writing 0; writing 1 has
no effect. Note that bit <29> is set whenever this bit is set.
CPU and System Registers E–23