Digital Equipment DECstation 5000/100 Series, Maintenance Manual

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The format of the diagnostic status field is
27 23 22 21 20 19 18 17 16
+-----------------+-----+----+----+----+----+-----+-----+
|
0 | BEV | TS | PE | CM | PZ | SwC | IsC |
+-----------------+-----+----+----+----+----+-----+-----+
5 1 1 1 1 1 1 1
BEV controls the location of UTLB miss and general
exception vectors (0 = normal, 1 = bootstrap).
TS indicates that TLB shut down occurred.
PE indicates that a cache parity error occurred. This bit
can be cleared by writing 1 to this bit position.
CM indicates whether a data cache miss occurred while the
system was in cache test mode (0 = hit, 1 = miss).
PZ controls the zeroing of cache parity bits (0 = normal, 1 =
parity forced to zero).
SwC controls the switching of the data and instruction
caches (0 = normal, 1 = switched).
IsC controls isolation of the cache (0 = normal, 1 = cache
isolated).
0 is unused (ignored on write, zero when read).
Status Register (R4000 Only)
The status register (SR) is a 32-bit read/write register that
contains the kernel/user mode, interrupt enable, and diagnostic
state of the processor. The SR contains the kernel, user,
supervisor, error level, exception level, and the interrupt enable
(IE) bit. These bits can also be directly read or written.
The status register has the following format:
31 28 27 26 25 24 16
+---------+---+---+---+----------------------------------+
|
CU |RP |FR |RE | DS |
+---------+---+---+---+----------------------------------+
4 1 1 1 9
CPU and System Registers E–11