Section 17 Watchdog Timer and Reset (WDT)
Rev. 1.00 Oct. 01, 2007 Page 654 of 1956
REJ09B0256-0100
17.4 Operation
17.4.1 Reset
request
Power-on reset and manual reset are available. These sources are follows.
(1) Power-on
reset
1. Reset sources
•
Input low level via
PRESET
pin.
•
The WDTCNT overflows when the WT/IT bit in the WDTCSR is 1, and the RSTS bit is 0.
•
The H-UDI reset occurs (For details, see section 42, User Debugging Interface (H-UDI)).
2. Branch destination address: H'A000 0000
3. Operation in branch
Exception code H'000 is set in the EXPEVT register. The VBR and SR registers are initialized,
and the program branches to PC =H'A000 0000. By initialization, the VBR register is set to
H'0000 0000. In the SR register, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0,
and the IMASK3 to IMASK0 bits (interrupt mask level) are set to B'1111.
The CPU and the peripheral modules are also initialized. For details, see the register descriptions
in each section.
When the power is turned on, be sure to input a low level to the
PRESET
pin. The
TRST
pin
should also be brought low level to initialize the H-UDI.
Power_on_reset()
{
EXPEVT = H'0000 0000;
VBR = H'0000 0000;
SR.MD
=
1;
SR.RB
=
1;
SR.BL
=
1;
SR.(I0-I3)
=
B'1111;
SR.FD
=
0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A000 0000;
}
Содержание SH7763
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Страница 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Страница 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Страница 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Страница 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Страница 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Страница 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Страница 686: ...Section 14 Direct Memory Access Controller DMAC Rev 1 00 Oct 01 2007 Page 620 of 1956 REJ09B0256 0100 ...
Страница 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Страница 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Страница 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Страница 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Страница 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Страница 1060: ...Section 23 Gigabit Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 994 of 1956 REJ09B0256 0100 ...
Страница 1062: ...Section 24 IP Security Accelerator SECURITY Rev 1 00 Oct 01 2007 Page 996 of 1956 REJ09B0256 0100 ...
Страница 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Страница 1184: ...Section 27 Serial Communication Interface with FIFO SCIF Rev 1 00 Oct 01 2007 Page 1118 of 1956 REJ09B0256 0100 ...
Страница 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Страница 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Страница 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Страница 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
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