Section 31 Multimedia Card Interface (MMCIF)
Rev. 1.00 Oct. 01, 2007 Page 1316 of 1956
REJ09B0256-0100
31.3.14 Transfer Clock Control Register (CLKON)
CLKON controls the transfer clock frequency and clock ON/OFF.
Bits CSEL[3:0] must be set to 0001 for the peripheral clock of 33.3 MHz in order to achieve a
16.7-Mbps transfer clock in the MMCIF. At this time, use a sufficiently slow clock for transfer in
open-drain type output in MMC mode.
In a command sequence, do not perform clock ON/OFF or frequency modification.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R
R
R
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
CLKON
—
—
—
CSEL[3:0]
Bit Bit
Name
Initial
Value R/W Description
7 CLKON
0 R/W
Clock
On
0: Fixes the transfer clock output from the MMC_CLK
pin to low level.
1: Outputs the transfer clock from the MMC_CLK pin.
6 to 4
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3 to 0
CSEL[3:0]
0000
R/W
Transfer Clock Frequency Select
0000: Setting prohibited
0001: Uses the 1/2-divided system clock as a transfer clock.
0010: Uses the 1/4-divided system clock as a transfer clock.
0011: Uses the 1/8-divided system clock as a transfer clock.
0100: Uses the 1/16-divided system clock as a transfer clock.
0101: Uses the 1/32-divided system clock as a transfer clock.
0110: Uses the 1/64-divided system clock as a transfer clock.
0111: Uses the 1/128-divided system clock as a transfer clock.
1000: Uses the 1/256-divided system clock as a transfer clock.
1001 to 1111: Setting prohibited
Содержание SH7763
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Страница 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Страница 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Страница 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Страница 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Страница 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Страница 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Страница 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Страница 686: ...Section 14 Direct Memory Access Controller DMAC Rev 1 00 Oct 01 2007 Page 620 of 1956 REJ09B0256 0100 ...
Страница 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Страница 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Страница 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Страница 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Страница 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Страница 1060: ...Section 23 Gigabit Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 994 of 1956 REJ09B0256 0100 ...
Страница 1062: ...Section 24 IP Security Accelerator SECURITY Rev 1 00 Oct 01 2007 Page 996 of 1956 REJ09B0256 0100 ...
Страница 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Страница 1184: ...Section 27 Serial Communication Interface with FIFO SCIF Rev 1 00 Oct 01 2007 Page 1118 of 1956 REJ09B0256 0100 ...
Страница 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Страница 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Страница 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Страница 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
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Страница 2026: ...SH7763 Hardware Manual ...