Section 36 USB Function Controller (USBF)
Rev. 1.00 Oct. 01, 2007 Page 1572 of 1956
REJ09B0256-0100
Figure 36.13 shows the normal operation of the USB function and firmware in isochronous-out
transfer.
EP4 has two up to 64-byte FIFOs, but the user can perform data transmission and read receive
data without being aware of this dual-FIFO configuration.
In isochronous transfer, transfer is occurred only once per one frame (1 ms). So, when SOF is
received, the FIFO buffer is switched automatically with hardware.
FIFO buffers are switched over by the SOF reception. Therefore, the FIFO buffer in which the
USB function receives the data from the host and the FIFO buffer in which the firmware reads the
receive data have different buffers, and a read and write of FIFO buffer are not competed.
Accordingly, the data read by the firmware is the data received in one frame before. The buffers of
FIFOs are switched over automatically by the SOF reception, so reading of data must be
completed within the frame.
The USB function receives data from the host after an out-token is received. If there is an error in
the data, set the internal TF flag to 1. If there is no error in the data, set the internal TS flag to 1.
In firmware, first, the processing routine of the isochronous transfer is called by SOF interrupt to
check the time stamp. Then data is read from the FIFO buffer. The flag information (TS, TF) is
read and decided if the data has an error. The flag information at this time represents the status of
the currently readable FIFO buffer.
SOF happens to be broken because of external cause during transmission from the host. In this
case, an operation flow is different from that in figure 36.13. As an example, figure 36.14 shows
the operation flow of a broken frame and a subsequent frame when SOF is broken once. When
SOF is broken, the FIFO buffer is not switched in current frame, and a time out interrupt is
occurred after time set by user has been elapsed. The USB function controller discards the data
which has been transmitted to the frame from the host.
The firmware detects the SOF break by the time out interrupt. In this case, the FIFO buffer
connected to the CPU does not read data since data has already been read. When the SOF interrupt
is occurred in the subsequent frame, the processing routine of the isochronous transfer is called
and the time stamps are compared. The time stamps do not much since the SOF break occurred in
the previous frame. Data is not read since the data in FIFO is not current one.
Содержание SH7763
Страница 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...
Страница 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Страница 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Страница 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Страница 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Страница 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Страница 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Страница 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Страница 686: ...Section 14 Direct Memory Access Controller DMAC Rev 1 00 Oct 01 2007 Page 620 of 1956 REJ09B0256 0100 ...
Страница 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Страница 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Страница 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Страница 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Страница 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Страница 1060: ...Section 23 Gigabit Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 994 of 1956 REJ09B0256 0100 ...
Страница 1062: ...Section 24 IP Security Accelerator SECURITY Rev 1 00 Oct 01 2007 Page 996 of 1956 REJ09B0256 0100 ...
Страница 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Страница 1184: ...Section 27 Serial Communication Interface with FIFO SCIF Rev 1 00 Oct 01 2007 Page 1118 of 1956 REJ09B0256 0100 ...
Страница 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Страница 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Страница 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Страница 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
Страница 2025: ......
Страница 2026: ...SH7763 Hardware Manual ...