Rev. 1.00 Oct. 01, 2007 Page xl of lxvi
Figure 6.9 Flowchart of Memory Access Using UTLB.............................................................. 160
Figure 6.10 Flowchart of Memory Access Using ITLB ............................................................. 161
Figure 6.11 Operation of LDTLB Instruction............................................................................. 164
Figure 6.12 Memory-Mapped ITLB Address Array................................................................... 173
Figure 6.13 Memory-Mapped ITLB Data Array ........................................................................ 174
Figure 6.14 Memory-Mapped UTLB Address Array ................................................................. 176
Figure 6.15 Memory-Mapped UTLB Data Array....................................................................... 177
Figure 6.16 Physical Address Space (32-Bit Address Extended Mode)..................................... 177
Figure 6.17 PMB Configuration ................................................................................................. 179
Figure 6.18 Memory-Mapped PMB Address Array ................................................................... 183
Figure 6.19 Memory-Mapped PMB Data Array......................................................................... 183
Section 7 Caches
Figure 7.1 Configuration of Operand Cache (OC) ..................................................................... 188
Figure 7.2 Configuration of Instruction Cache (IC) ................................................................... 189
Figure 7.3 Configuration of Write-Back Buffer ......................................................................... 201
Figure 7.4 Configuration of Write-Through Buffer.................................................................... 201
Figure 7.5 Memory-Mapped IC Address Array ......................................................................... 207
Figure 7.6 Memory-Mapped IC Data Array............................................................................... 208
Figure 7.7 Memory-Mapped OC Address Array........................................................................ 210
Figure 7.8 Memory-Mapped OC Data Array ............................................................................. 211
Figure 7.9 Store Queue Configuration........................................................................................ 212
Section 9 Interrupt Controller (INTC)
Figure 9.1 Block Diagram of INTC............................................................................................ 234
Figure 9.2 Example of IRL Interrupt Connection....................................................................... 293
Figure 9.3 On-chip Module Interrupt Priority ............................................................................ 296
Figure 9.4 Interrupt Operation Flowchart................................................................................... 306
Figure 9.5 Example of Interrupt Handling Routine .................................................................... 309
Section 10 SuperHyway Bus Bridge (SBR)
Figure 10.1 SBR Block Diagram................................................................................................ 313
Figure 10.2 Bus Arbitration by the SBR..................................................................................... 317
Section 11 Local Bus State Controller (LBSC)
Figure 11.1 LBSC Block Diagram ............................................................................................. 321
Figure 11.2 Correspondence between Virtual Address Space and External Memory Space...... 325
Figure 11.3 External Memory Space Allocation ........................................................................ 327
Figure 11.4 Basic Timing of SRAM Interface............................................................................ 366
Figure 11.5 Example of 32-Bit Data-Width SRAM Connection................................................ 367
Figure 11.6 Example of 16-Bit Data-Width SRAM Connection................................................ 368
Figure 11.7 Example of 8-Bit Data-Width SRAM Connection.................................................. 368
Содержание SH7763
Страница 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...
Страница 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Страница 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Страница 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Страница 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Страница 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Страница 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Страница 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Страница 686: ...Section 14 Direct Memory Access Controller DMAC Rev 1 00 Oct 01 2007 Page 620 of 1956 REJ09B0256 0100 ...
Страница 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Страница 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Страница 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Страница 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Страница 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Страница 1060: ...Section 23 Gigabit Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 994 of 1956 REJ09B0256 0100 ...
Страница 1062: ...Section 24 IP Security Accelerator SECURITY Rev 1 00 Oct 01 2007 Page 996 of 1956 REJ09B0256 0100 ...
Страница 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Страница 1184: ...Section 27 Serial Communication Interface with FIFO SCIF Rev 1 00 Oct 01 2007 Page 1118 of 1956 REJ09B0256 0100 ...
Страница 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Страница 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Страница 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Страница 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
Страница 2025: ......
Страница 2026: ...SH7763 Hardware Manual ...