Rev. 1.00 Oct. 01, 2007 Page lvi of lxvi
Figure 43.61 SIOF Transmission/Reception Timing
(Master Mode 1, Sampling at the Falling Edge) ................................................. 1885
Figure 43.62 SIOF Transmission/Reception Timing
(Master Mode 1, Sampling at the Rising Edge) .................................................. 1885
Figure 43.63 SIOF Transmission/Reception Timing
(Master Mode 2, Sampling at the Falling Edge) ................................................. 1886
Figure 43.64 SIOF Transmission/Reception Timing
(Master Mode 2, Sampling at the Rising Edge) .................................................. 1886
Figure 43.65 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) .............. 1887
Figure 43.66 SIM Module Signal Timing ................................................................................ 1888
Figure 43.67 MMCIF Transmit Timing ................................................................................... 1889
Figure 43.68 MMCIF Receive Timing (Sampling at the Rising Edge).................................... 1890
Figure 43.69 HAC Cold Reset Timing ..................................................................................... 1891
Figure 43.70 HAC SYNC Output Timing ................................................................................ 1891
Figure 43.71 HAC Clock Input Timing.................................................................................... 1892
Figure 43.72 HAC Interface Module Signal Timing ................................................................ 1892
Figure 43.73 SSI Clock Input/Output Timing .......................................................................... 1893
Figure 43.74 SSI Transmit Timing (1) ..................................................................................... 1893
Figure 43.75 SSI Transmit Timing (2) ..................................................................................... 1894
Figure 43.76 SSI Receive Timing (1)....................................................................................... 1894
Figure 43.77 SSI Receive Timing (2)....................................................................................... 1894
Figure 43.78 USB Clock Timing.............................................................................................. 1895
Figure 43.79 LCDC Module Signal Timing............................................................................. 1897
Figure 43.80 GPIO Timing....................................................................................................... 1897
Figure 43.81 TCK Input Timing............................................................................................... 1898
Figure 43.82
PRESET
Hold Timing......................................................................................... 1899
Figure 43.83 H-UDI Data Transfer Timing.............................................................................. 1899
Figure 43.84
ASEBRK
Pin Break Timing................................................................................ 1899
Figure 43.85 Output Load Circuit ............................................................................................ 1901
Figure 43.86 Load Capacitance - Delay Time .......................................................................... 1902
Appendix
Figure B.1 Instruction Prefetch................................................................................................. 1905
Figure D.1 Schematic Diagram of External Circuits ................................................................ 1908
Figure E.1 Connection Example of Bypass Capacitors for Analog Power Supply .................. 1911
Figure F.1 Package Dimensions (449-Pin) ............................................................................... 1912
Figure J.1 Overall View of Simulation Model (with heat sink)................................................ 1945
Figure J.2 Heat Sink Model...................................................................................................... 1946
Содержание SH7763
Страница 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...
Страница 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Страница 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Страница 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Страница 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Страница 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Страница 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Страница 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Страница 686: ...Section 14 Direct Memory Access Controller DMAC Rev 1 00 Oct 01 2007 Page 620 of 1956 REJ09B0256 0100 ...
Страница 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Страница 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Страница 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Страница 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Страница 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Страница 1060: ...Section 23 Gigabit Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 994 of 1956 REJ09B0256 0100 ...
Страница 1062: ...Section 24 IP Security Accelerator SECURITY Rev 1 00 Oct 01 2007 Page 996 of 1956 REJ09B0256 0100 ...
Страница 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Страница 1184: ...Section 27 Serial Communication Interface with FIFO SCIF Rev 1 00 Oct 01 2007 Page 1118 of 1956 REJ09B0256 0100 ...
Страница 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Страница 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Страница 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Страница 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
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Страница 2026: ...SH7763 Hardware Manual ...