Section 26 I
2
C Bus Interface (IIC)
Rev. 1.00 Oct. 01, 2007 Page 1042 of 1956
REJ09B0256-0100
Bit
Bit Name
Initial Value
R/W
Description
7 to 2
SCGD
All 0
R/W
SCL Clock Generation Divider
When operating in master mode, the SCL
clock is generated from the internal clock using
SCGD as the ratio. The slave will also operate
on the clock generated from the internal clock
when SCL is held low to hold the bus up when
an overflow occurs. SCGD must be specified in
both master and slave modes. The formula
expressing the relationship is:
Equation 2 SCL rate calculation
SCLfreq = IICck / (20 + (SCGD
*
8))
IICck:
I
2
C internal clock frequency
Suggested settings for CDF and SCGD for
various CPU speeds and the two I
2
C bus
speeds are given in table 26.4.
1, 0
CDF
All 0
R/W
Clock Division Factor
The internal clock used in most blocks in the
I
2
C module is a divided peripheral clock. The
internal I
2
C clock is generated from the
peripheral clock using the CDF as the division
ratio:
Equation 1 I
2
C internal clock frequency
calculation
IICck = Pck0 / (1 + CDF)
Pck0: Peripheral clock
The minimum time to ensure adequate setup
and hold times on the SDA line relative to the
SCL line on the bus.
The clock frequency is to ensure that the glitch
filtering will operate with glitches of up to 50 ns
as described in the fast mode I
2
C specification.
Note: CDF must be set so that the clock frequency (IICck) is lower than 20 MHz.
Содержание SH7763
Страница 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...
Страница 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Страница 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Страница 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Страница 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Страница 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Страница 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Страница 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Страница 686: ...Section 14 Direct Memory Access Controller DMAC Rev 1 00 Oct 01 2007 Page 620 of 1956 REJ09B0256 0100 ...
Страница 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Страница 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Страница 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Страница 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Страница 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Страница 1060: ...Section 23 Gigabit Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 994 of 1956 REJ09B0256 0100 ...
Страница 1062: ...Section 24 IP Security Accelerator SECURITY Rev 1 00 Oct 01 2007 Page 996 of 1956 REJ09B0256 0100 ...
Страница 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Страница 1184: ...Section 27 Serial Communication Interface with FIFO SCIF Rev 1 00 Oct 01 2007 Page 1118 of 1956 REJ09B0256 0100 ...
Страница 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Страница 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Страница 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Страница 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
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Страница 2026: ...SH7763 Hardware Manual ...