Section 30 SIM Card Module (SIM)
Rev. 1.00 Oct. 01, 2007 Page 1254 of 1956
REJ09B0256-0100
Bit Bit
Name
Initial
Value R/W Description
5 ORER 0
R/W
Overrun Error
Indicates that an overrun error occurred during reception,
resulting in abnormal termination.
0: Indicates that reception is in progress, or that reception
was completed normally
*
1
[Clearing conditions]
•
On reset
•
When 0 is written to the ORER bit
1: Indicates that an overrun error occurred during
reception
*
2
[Setting condition]
When the RDRF bit is set to 1 and the next serial reception
is completed.
Notes:
1. When the RE bit in SCSCR is cleared to 0, the
ORER flag is unaffected and the previous state
is retained.
2. In SCRDR, the received data before the
overrun error occurred is lost, and the data that
had been received at the time when the
overrun error occurred is retained. Further, with
the ORER bit set to 1, subsequent serial
reception cannot be continued.
4 ERS 0
R/W
Error Signal Status
Indicates the status of error signals returned from the
receive side during transmission. In T = 1 mode, this flag is
not set.
0: Indicates that an error signal indicating detection of a
parity error was not sent from the receive side
[Clearing conditions]
•
On reset
•
When 0 is written to the ERS bit
1: Indicates that an error signal indicating detection of a
parity error was sent from the receive side
[Setting condition]
When an error signal is sampled.
Note:
Even if the TE bit in SCSCR is cleared to 0, the
ERS flag is unaffected, and the previous state is
retained.
Содержание SH7763
Страница 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...
Страница 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Страница 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Страница 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Страница 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Страница 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Страница 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Страница 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Страница 686: ...Section 14 Direct Memory Access Controller DMAC Rev 1 00 Oct 01 2007 Page 620 of 1956 REJ09B0256 0100 ...
Страница 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Страница 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Страница 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Страница 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Страница 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Страница 1060: ...Section 23 Gigabit Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 994 of 1956 REJ09B0256 0100 ...
Страница 1062: ...Section 24 IP Security Accelerator SECURITY Rev 1 00 Oct 01 2007 Page 996 of 1956 REJ09B0256 0100 ...
Страница 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Страница 1184: ...Section 27 Serial Communication Interface with FIFO SCIF Rev 1 00 Oct 01 2007 Page 1118 of 1956 REJ09B0256 0100 ...
Страница 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Страница 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Страница 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Страница 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
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Страница 2026: ...SH7763 Hardware Manual ...