Section 26 I
2
C Bus Interface (IIC)
Rev. 1.00 Oct. 01, 2007 Page 1026 of 1956
REJ09B0256-0100
26.2 Input/Output
Pins
Table 26.1 lists the pins used in the I
2
C bus interface.
Table 26.1 Pin Configuration
Channel Pin
Name
I/O
Description
IIC0_SCL I/O
I
2
C serial clock input/output pin
*
0
IIC0_SDA I/O
I
2
C serial data input/output pin
*
IIC1_SCL I/O
I
2
C serial clock input/output pin
*
1
IIC1_SDA I/O
I
2
C serial data input/output pin
*
Note:
*
The SCL and SDA pins are open drain pins (3.3 V).
26.3 Register
Descriptions
Table 26.2 shows the IIC register configuration. Table 26.3 shows the register state in each
operating mode.
Table 26.2 Register Configuration
Channel Register Name
Abbreviation
R/W
Area P4
Address
*
1
Area 7
Address
*
1
Access
Size
Slave control register 0
ICSCR0
R/W
H'FFE7 0000 H'1FF7 0000 8
Master control register 0
ICMCR0
R/W
H'FFE7 0004 H'1FF7 0004 8
Slave status register 0
ICSSR0
R/(W)
*
2
H'FFE7 0008 H'1FF7 0008 8
Master status register 0
ICMSR0
R/(W)
*
3
H'FFE7 000C H'1FF7 000C 8
Slave interrupt enable
register 0
ICSIER0
R/W
H'FFE7 0010 H'1FF7 0010 8
Master interrupt enable
register 0
ICMIER0
R/W
H'FFE7 0014 H'1FF7 0014 8
Clock control register 0
ICCCR0
R/W
H'FFE7 0018 H'1FF7 0018 8
Slave address register 0
ICSAR0
R/W
H'FFE7 001C H'1FF7 001C 8
Master address register 0 ICMAR0
R/W
H'FFE7 0020 H'1FF7 0020 8
Receive data register 0
ICRXD0
R/W
H'FFE7 0024 H'1FF7 0024 8
0
Transmit data register 0
ICTXD0
R/W
H'FFE7 0024 H'1FF7 0024 8
Содержание SH7763
Страница 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...
Страница 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Страница 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Страница 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Страница 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Страница 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Страница 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Страница 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Страница 686: ...Section 14 Direct Memory Access Controller DMAC Rev 1 00 Oct 01 2007 Page 620 of 1956 REJ09B0256 0100 ...
Страница 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Страница 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Страница 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Страница 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Страница 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Страница 1060: ...Section 23 Gigabit Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 994 of 1956 REJ09B0256 0100 ...
Страница 1062: ...Section 24 IP Security Accelerator SECURITY Rev 1 00 Oct 01 2007 Page 996 of 1956 REJ09B0256 0100 ...
Страница 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Страница 1184: ...Section 27 Serial Communication Interface with FIFO SCIF Rev 1 00 Oct 01 2007 Page 1118 of 1956 REJ09B0256 0100 ...
Страница 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Страница 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Страница 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Страница 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
Страница 2025: ......
Страница 2026: ...SH7763 Hardware Manual ...