Renesas SH7763, Руководство по оборудованию

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Section 9 Interrupt Controller (INTC)
Rev. 1.00 Oct. 01, 2007 Page 276 of 1956
REJ09B0256-0100
9.3.18 Interrupt Mask Register (INT2MSKR)
INT2MSKR is a 32-bit readable/writable register that sets masking for each source indicated in
the interrupt source register. Interrupts whose corresponding bits in INT2MSKRG are set to 1 are
not notified to the CPU.
INT2MSKR is initialized to H'FFFF FFFF (mask state) by a reset.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R R/W R/W R R/W R R R R R R
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R R/W R/W R R R R/W R/W R/W R/W
GPIO
SSI0 MMCIF
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2
PCIC1 PCIC0 HAC CMT
DMAC H-UDI SCIF1 SCIF0 WDT RTC TMU1 TMU0
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
− − − − − − − −
− − − −
Bit Bit Name
Initial
Value R/W
Function Description
31 to 26 — All 1 R These bits are always read as 1.
The write value should always be
1.
25 GPIO 1 R/W Masks GPIO interrupts
24 — 1 R This bit is always read as 1. The
write value should always be 1.
23 SSI0 1 R/W Masks SSI0 interrupts
22 MMCIF 1 R/W Masks MMCIF interrupts
21 — 1 R This bit is always read as 1. The
write value should always be 1.
20 SIOF0 1 R/W Masks SIOF0 interrupts
19 PCIC5 1 R/W Masks PCIC5 interrupts
18 PCIC4 1 R/W Masks PCIC4 interrupts
17 PCIC3 1 R/W Masks PCIC3 interrupts
16 PCIC2 1 R/W Masks PCIC2 interrupts
15 PCIC1 1 R/W Masks PCIC1 interrupts
14 PCIC0 1 R/W Masks PCIC0 interrupts
Masks interrupts
for each peripheral
module.
[When writing]
0: Invalid
1: Interrupts are
masked
[When reading]
0: No mask setting
1: Mask setting