Toshiba TX49 TMPR4937, Manual

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Chapter 3 Signals
3-6
3.1.6 Serial I/O Interface Signals
Table 3.1.6 Serial I/O Interface Signals
Signal Name Type Description Initial State
CTS [1:0] * Input
PU
SIO Clear to Send
CTS
* signals.
Input
RTS [1:0] * Output SIO Request to Send
RTS
* signals.
All Low
RXD[1:0] Input
PU
SIO Receive Data
Serial data input signals. Input
TXD[1:0] 3-state
Output SIO Transmit Data
Serial data output signals. All High
SCLK Input
PU
External Serial Clock
SIO clock input signal. SIO0 and SIO1 share this signal. Input
3.1.7 Timer Interface Signals
Table 3.1.7 Timer Interface Signals
Signal Name Type Description Initial State
TIMER[1:0] Output Timer Output
Timer output signals.
All High
TCLK Input
PU
External Timer Clock
Timer input clock signal. TMR0, TMR1, and TMR2 share this signal. Input
WDRST * OD output Watchdog Reset
Watchdog reset output signal.
Hi-Z
3.1.8 Parallel I/O Interface Signals
Table 3.1.8 Parallel I/O Interface Signals
Signal Name Type Description Initial State
PIO[15:8] Input/output
PU
PIO Ports[15:8]
Parallel I/O signals.
PIO[15:8] share pins with the SDRAM ECC/parity signals (CB[7:0]). The boot
configuration signal on the ADDR[18] pin selects between PIO[5:8] and CB[7:0] (refer to
Section “3.3 Pin multiplex”). Input
PIO[7:0] Input/output
PU
PIO Ports[7:0]
Parallel I/O signals.
PIO[4:2] share pins with the AC-link interface signals (SDOUT, SDIN[0], and BITCLK).
The boot configuration signal on the ADDR[9] pin selects between PIO[4:2] and AC-link
interface signals (refer to Section “3.3 Pin multiplex”). Input
(other than
PIO[4])
Selected by
ADDR[9]
(PIO[4] only)
L: Input
H: All Low