Toshiba TX49 TMPR4937, Manual

Page: 517 / 553

Chapter 21 Electrical Characteristics
21-11
21.5.7 PCI EEPROM Interface AC characteristics
(Tc = 0 ~ 70
°
C, V
CCIO
= 3.3 V
±
0.2 V, V
CCInt
= 1.5 V
±
0.1 V, V
SS
= 0 V)
Item Symbol Conditions Min. Max. Unit
EEPROM_SK High Time
t
HIGH_EPSK
C
L
=50 pF 500
⎯
ns
EEPROM_SK Low Time
t
LOW_EPSK
C
L
=50 pF 500
⎯
ns
EEPROM_DO Output Delay Time
* 1)
t
VAL_EPDO
C
L
=50 pF
⎯
100 ns
EEPROM_DI Input Setup Time
t
SU_EPDI
100
⎯
ns
EEPROM_DI Input Hold Time
t
HO_EPDI
100
⎯
ns
EEPROM_CS Output Delay Time
t
VAL_CS
C
L
=50 pF 100
⎯
ns
* 1) The TX4937 controls EEPROM and its control signal synchronous to the falling edge of
EEPROM_SK. Since the EEPROM operates at the rising edge of EEPROM_SK, you do not have
to take the MIN side of EEPROM_DO into account.
Figure 21.5.8 Timing Diagram: PCI EEPROM Interface
21.5.8 DMA Interface AC characteristics
(Tc = 0 – 70
°
C, V
CCIO
= 3.3 V
±
0.2 V, V
CCInt
= 1.5 V
±
0.1 V, V
SS
= 0 V)
Item Symbol Conditions Min. Max. Unit
DMADONE
*
Delay t
VAL_DONE
C
L
=50 pF
SYSCLK (C
L
=50 pF) reference
⎯ 12 ns
Boot configuration
ADDR[2]=H t
MCP
×
1.1
⎯
ns DMADONE
*
Input Pulse Width Time t
PW_DONE
Boot configuration
ADDR[2]=L 1/4
×
t
MCP
×
1.1
⎯
ns
Figure 21.5.9 Timing Diagram: DMA Interface
EEPROM_SK
EEPROM_DO
t
VAL_EPDO
t
HIGH_EPSK
EEPROM_DI
t
SU_EPDI
EEPROM_CS
t
VAL_EPCS
t
LOW_EPSK
t
HO_EPDI
DMADONE *
t
PW_DONE
SYSCLK
DMADONE *
t
VAL_DONE